System Validation Engineer IV : 19-04209

San Jose, CA 95134

Posted: 10/02/2019 Job Category: Hardware Engineering Job Number: 12664820
Primary Skills: FPGA design, Data Center/Cloud-oriented, Verilog / SystemVerilog, TCL/Perl/Python
Duration: 4 Months
Contract Type: W2 Only


Job Description:
  • This position is in System Validation team in Programmable Solutions Group. Client FPGA based solutions are accelerating Data Center Applications as well as Networking Infrastructure.
  • To enable easy adoption, Programmable Solutions Group (PSG) is building Platform Solutions for workload acceleration as well as customizable solutions that can be tailored to meet our customer needs.
  • Solution Validation team within Platform Validation Engineering (PVE) is looking for FPGA design engineers for validating platform acceleration stack with innovative FPGA based designs.
  • As a FPGA Design Engineer, you will have an integral role in designing and delivering innovative FPGA solutions to exercise the system level features of the Platform acceleration stack.
  • You will be responsible for developing the FPGA design using Client’s latest FPGA products/technologies targeting datacenter/Cloud-oriented computing products.
  • This role covers all aspects of FPGA design development process including: design planning/architecture, developing platform/system functionalities in FPGA RTL using Verilog / SystemVerilog, RTL simulation, logic optimization, synthesis, FPGA floorplanning, timing closure and documentation. A sound understanding of RTL and FPGA design practices is important.
  • The ideal candidate will need to be able to demonstrate the following behaviors, Strong track record of taking initiative and drive projects to completion, strong communication skills and ability to influence and work across large teams across sites.
 Qualifications/skill sets required, not limited to the following:
  • 10+ years of experience in the following:
  • Hands-on FPGA development experience including synthesis, placement, optimization and timing closure.
  • Hands-on Verliog and/or SystemVerilog experience.
  • Experience with simulation tools like modelsim for design verification.
  • Experience with scripting languages TCL, or Perl, or Python.
  • Experience with design verification, debug & also validation at platform/system level.
Preferred Skill sets:
  • System architecture understanding and exposure to Linux device drivers will be helpful.
  • Experience with interface and memory protocols such as PCIe, 10G/40G/100G Ethernet, and DDR4 helpful.
  • Experience with Client/Altera Quartus II software.
  • Exposure to software programming C/C++ will be helpful
  • B.S. or M.S. in Electrical Engineering, Computer Engineering or an equivalent field.
   To follow up with any questions, please contact Sanket Yede at 408-907-2249 

Akraya is an award-winning IT staffing firm and the staffing partner of choice for many leading companies across the US. We offer comprehensive benefits including Health Insurance (medical, dental, and vision), Cafeteria Plan (HSA, FSA, and dependent care), 401(k) (enrollment subject to eligibility), and Sick Pay (varies based on city and state laws).
 
If this position is not quite what you're looking for, visit akraya.com and submit a copy of your resume. We will get to work finding you a job that is a better fit at one of our many amazing clients.
 
Akraya is committed to equal treatment and opportunity in all aspects of recruitment, selection, and employment without regard to gender, race, religion, national origin, ethnicity, disability, gender identity/expression, sexual orientation, veteran or military status, or any other category protected under the law. Akraya is an equal opportunity employer; committed to a community of inclusion, and an environment free from discrimination, harassment, and retaliation. 

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