FPGA/RTL Design Engineer IV : 19-03014

Hudson, MA 01749

Posted: 06/27/2019 Job Category: Hardware Engineering Job Number: 12362804
Akraya is looking for a FPGA/RTL Design Engineer IV for one of our leading clients.To be considered, please apply or call Pooja at 408-907-2233.
 
We are an award-winning staffing firm that works with many leading technology-based companies around the world. The benefits offered to our employees include Health Insurance (Medical, Dental, and Vision), Cafeteria Plan (HSA, FSA, and dependent care), 401(k) (enrollment subject to eligibility), and Sick Pay (varies based on city and state laws). If this position is not quite what you’re looking for, visit akraya.com and submit a copy of your resume. We will get to work finding you a job that is a better match at one of our many amazing clients.

Primary FPGA, RTL(Verilog, synthesis, VCS), USB, microprocessor,
Duration: 12+ Months
Contract Type: W2 Only

Responsibilities: 

Candidate will be working on FGPA design with a very small team. He or she will be developing the micro-architecture and RTL with ownership of key IP blocks. This team will be driving Proof-of-Concept ideas to help drive silicon development in the Data Center. The candidate must be well versed in standard RTL practices, FPGA design (preferably Altera/Client), and standard RTL design flows (Verilog, synthesis, VCS). There may be opportunities for the candidate to help with the design validation and documentation as well.

Top Skills:
Design Validation - Solid recent PCIe DV Experience, coupled with OVM/UVM methodologies. It would be a plus if they had experience with FPGAs as well.

Job Description/Skills needed:
  • 5 + years of FPGA design experience, preferably Xilinx FPGAs. Experience with going through 3-5 Iarge FPGAs through complete design cycle, from RTL to timing driven synthesis to place & route, static timing analysis. 5+ years of RTL, - Verilog, System - Verilog, - VHDL experience 5+ years of FPGA design experience, preferably Xilinx FPGAs
  • Comfortable with Perl and C Expertise with Synplify, - VCS, Modelsim and Xilinx Client tool
  • Experience with USB, microprocessor, SDIO/SD/eMMC, Audio at RTL Ievel will be plus Logic analyzer, PCB/hardware bring up and debug will be plus ?Protocol Ievel RTL implementation knowledge on USB/OTG, PCIe, eMMC, SDIO/SD, ARC or some microcontroller, SPI, DDR2 memory.
  • Expert in computer architecture and some understanding on PCB board Ievel hardware.
Minimum Educational Requirement:
Bachelor's Degree or Master's Degree in CS, EE or other closely related field.

Please apply directly with your updated resume or call Pooja Rai at 408-907-2233

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