ASIC Physical Designers III : 19-02941

Chandler, AZ 85226

Posted: 07/01/2019 Job Category: Hardware Engineering Job Number: 12340685
Akraya is looking for an ASIC Physical Designers III for one of our leading clientsTo be considered, please apply or call Sanket Yede at 408-907-2249

We are an award-winning staffing firm that works with many leading technology-based companies around the world. The benefits offered to our employees include Health Insurance (Medical, Dental, and Vision), Cafeteria Plan (HSA, FSA, and dependent care), 401(k) (enrollment subject to eligibility), and Sick Pay (varies based on city and state laws). If this position is not quite what you’re looking for, visit akraya.com and submit a copy of your resume. We will get to work finding you a job that is a better match at one of our many amazing clients.

Primary Skills: ASIC, DFT/scan, synthesis, APR, STA, LVS and debug
Duration: 3 Months
Contract Type: W2 Only


Job Description:
  • Previous Client experience is a big plus! Must have strong skills, educational degree noted below is required.
  • 1 CW resource with FC layout ILD layout experience to work on FC layout/integration.
  • Experimental work to run pin assignment w/ different option (groups vs full) and collect CPU and memory runtime.
  • Experimental work to run route with various options (w and w/o route guide; blockages, etc.) and collect CPU and memory runtime.
  • RDL(Bump/M15/M14) route automation
Required Skills:
  • Experience in handling end2end execution of complex SoC with focus on Full chip floor-planning as primary responsibility.
  • Preferably experience in TSMC N7 technology flows - Timing closure, DRC, LVS, Antenna checks, IR drop, multi voltage checks etc.
  • Expertise in Synopsys suite (IC Compiler, StarRCXT).
  • Performing floor-planning and routing studies and implementation
  • Perform Physical verification activities at full chip level.
General Required Skills:
  • ASIC and SoC design experience, Physical design CAD flows and Design convergence. Includes synthesis, APR, STA, LVS and debug.
Preferred Skills:
  • Verilog RTL skills, Synthesis and Timing analysis experience, Synopsys ICC, DFT tools, scripting in PERL and Shell. Unix. Communication and team skills.
  • Minimum Educational Requirement: BS +experience, MS + experience.
  • Client component design experience preferred.
Minimum Educational Requirement:
  • BS +experience, MS + experience. Client component design experience preferred.
  Please apply directly with your update resume or call Sanket Yede at 408-907-2249

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